LFE3-70EA-8FN672I Programmable Logic Ic Read Only Memory 66.5K LUTs 380 I/O

LFE3-70EA-8FN672I Programmable Read Only Memory 66.5K LUTs 380 I/O SERDES1.2V-8Spd IND

Specifications

Description

The LatticeECP3 (EConomy Plus Third generation) family of FPGA devices is optimized to deliver

high performance features such as an enhanced DSP architecture, high speed SERDES and high

speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved

through advances in device architecture and the use of 65 nm technology making the devices

suitable for high-volume, high-speed, low-cost applications. The LatticeECP3 device family expands

look-up-table (LUT) capacity to 149 K logic elements and supports up to 586 user I/O.

The LatticeECP3 device family also offers up to 320 18 x 18 multipliers and a wide range of parallel I/O

standards. The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind.

The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks

such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked

Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced

configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous

logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including

DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also features high speed SERDES with dedicated

PCS functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured

to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII)

and CPRI. Transmit Pre-emphasis and Receive Equalization settings make the SERDES suitable for transmission

and reception over various forms of media. The LatticeECP3 devices also provide flexible, reliable and secure

configuration options, such as dual-boot capability, bitstream encryption, and TransFR field upgrade features.

Features

• Higher Logic Density for Increased System Integration

• 17 K to 149 K LUTs

• 116 to 586 I/O

• Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10- bit SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

• Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI,

SMPTE 3G and Serial RapidIO

• sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

• Half 36x36, two 18x18 or four 9x9 multipliers

• Advanced 18x36 MAC and 18x18 Multiply- Multiply-Accumulate (MMAC) operations

• Flexible Memory Resources

• Up to 6.85 Mbits sysMEM™ Embedded Block RAM (EBR)

• 36 K to 303 K bits distributed RAM

• sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

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