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XC2C64A-7VQG100C Programmable FPGA Complex Programmable Logic Devices XC2C64A
Specifications
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| Product Category: | CPLD - Complex Programmable Logic Dev |
| XC2C64A | |
| SMD/SMT | |
| VQFP-100 | |
| 1.8 V | |
| 64 | |
| 64 I/O | |
| 1.9 V | |
| 1.7 V | |
| 0 C | |
| + 70 C | |
| 263 MHz | |
| 4.6 ns | |
| Number of Logic Array Blocks - LABs: | 4 |
| Operating Supply Current: | 17 uA |
Description
Xilinx CoolRunner™-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3 family in a single CPLD. This means that the exact same parts can be used for high-speed data communications/ computing systems and leading edge portable products, with the added benefit of In System Programming. Low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. Clocking techniques and other power saving features extend the users’ power budget. The design features are supported starting with Xilinx ISE® 4.1i WebPACK tool.
Features
• Optimized for 1.8V systems - Industry’s fastest low power CPLD - Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface
- On-The-Fly Reconfiguration (OTF)
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Multiple I/O banks on all devices
- Unsurpassed low power management
· DataGATE external signal control
- Flexible clocking modes
·Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK - Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
- Abundant product term clocks, output enables and set/resets
- Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on select I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts
CoolRunner-II CPLD Family Parameters
Trading Guide
| Shipping | Delivery period | For in-stock parts, orders are estimated to ship out in 3 days.Once shipped, estimated delivery time depends on the below carriers you chose: |
| Shipping rates | After confirming the order, we will evaluate the shipping cost based on the weight of the goods | |
| Shipping option | We provide DHL, FedEx, EMS, SF Express, and Registered Air Mail international shipping. | |
| Shipping tracking | We will notify you by email with tracking number once order is shipped. | |
| Returning warranty | Returning | Returns are normally accepted when completed within 30 days from date of shipment.Parts should be unused and in original packaging.Customer has to take charge for the shipping. |
| Warranty | All Retechip purchases come with a 30-day money-back return policy, This warranty shall not apply to any item where defects have been caused by improper customer assembly, failure by customer to follow instructions, product modification, negligent or improper operation | |
| Ordering | Payment | T/T,PayPal, Credit Card includes Visa, Master, American Express. |
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